As with most nodules I design, I just needed something. This time I was in need of a sample and hold module to silence the inner R2D2 in me. I had the circuit already implemented in various other, more complex modules, so it wasn’t a big adventure in getting the circuit designed. No real war stories here about obstacles needed to be conquered, personal development, valuable insights and all that motivational crap. Nevertheless I still felt it could make for a valuable blog post, and it was too long ago I posted something anyways.
So, how does it work?
A sample & hold circuit is fairly simple. An incoming signal gets sampled when a trigger pulse arrives at the trigger input. The circuit holds that value until it receives the next trigger. Easy peasy, takes only a handful of components. Now, there are 2 things of notable importance in the circuit, how fast a sample can be acquired — acquisition time — and how long it can be held.
At the core is a holding capacitor ( C9 ) in between 2 opamps ( U1A & U1B ) which are configured as voltage followers. The JFET ( Q1 ) will act as a switch. When Q1 is open, the capacitor will quickly adjust to the current voltage level out of U1A, when Q2 closes up again the holding capacitor will keep its voltage steady as – ELI5 – the electricity stored in the capacitor basically has no place to go. U1B is an opamp and has a theoretical infinite impedance, a fancy way of saying that it if you measure the resistance between the opamp’s input and ground it will show “OL” on your multimeter. At the other side of the holding capacitor there is the JFET, which has a very high off resistance. There is simply no low resistance path which the capacitor can use to discharge, so it keeps its charge. However, the world is far from perfect and the capacitor will slowly discharge over time due to theory and reality never really agreeing on things like physics and stuff. Capacitor type, capacitor value, JFETS used and opamps all play a role.
Every component has its reason to be there and influences the whole circuit to some degree, as per usual. So now the nit-picking begins, plowing through the datasheets to get a reasonably decent working circuit for at a reasonable size and at a reasonable price. But let’s consider our use case for a moment first, so we know what ‘reasonable’ actually entails.
There are 2 big things which matter most, the maximum rate at which the circuit can be triggered to sample, and how steady the sample is over time. Our trigger rate is on average probably somewhere at a few times a second for most uses of a S&H circuit, so that’s a few Hz, but using a S&H circuit as some sort of sample rate reducer is always fun, so it should handle audio rates as well. Anything between 10-20kHz seems like an acceptable upper limit. Above that little of interest happens when it comes to audio applications. At 20kHz a single cycle of a waveform takes 50µs, so an acquisition time between 50µs to 100µs seems adequate.
How long we should be able of maintaining a sample is a bit harder to quantify. We can’t really get around the voltage loss over time, aka the droop ( I didn’t invented the term, although I wish I did ). So how much voltage drop can we tolerate over a second. In a typical modular system pitch CV is where exact voltages do matter. On the v/octave scale each semitone is 83mV apart, that’s not a lot. According to some research I found through google (isn’t google amazing like that) we won’t reliably detect pitch changes within 5 cent either way of perfect pitch.
A cent is 1/50th of a semitone, so that makes 1,66mV/Cent*. A cent is 1/100th of a semitone, so that makes 0,83mV/Cent. So we need to keep the ‘droop’ lower as 4,15mV during our target time frame. If we can keep it within that limit for several seconds, that would be great.
*Thanks to bringing the mistake to my attention.
The input trigger gets sanitised by passing through a high pass filter and then through an opamp ( U2A ) configured as a comparator. The setup of the highpass filter ( C5/R5 ), and to some extend the slope time of the opamp will determine the length of the pulse. The JFET only needs nanoseconds to react according to the datasheet, so that’s not an issue since it’s an order of magnitude lower then the time-frames we’re aiming for. The limiting factor in our design is the time it takes for C9 to fully charge. I couldn’t find a way to calculate it quickly in this circuit so I simply measured it. It took about 22µs. Fiddling a bit around with the high pass filter and trying out some values I came to a pulse of around 57µs ( between -12V and +12V ) to open up the JFET gate. A bit more as twice the needed time for the capacitor charging and it gives enough margin to account for all tolerances in the circuit. At those speeds we can handle trigger speeds above 10kHz without much issue, I estimate things will start to stop working at 16kHz more or less. But that’s well in our intended range.
Measuring droop is a bit harder. It are quite small differences in voltage over a relatively long time and I don’t have a fancy calibrated multimeter capable of reliably measuring tenths of a millivolt. So, stopwatch and voltage meter it is. It took approximately 30 seconds to drop 0.01V, aka 10mV. The value of the capacitor does matter. The smaller it is, the faster it discharges ( but also the faster it charges) so we kind of need to chose a value that can still charge reliably within our acquisition time of 57µs but is as big as possible. I stranded at a 220nF polyester one. 100nF did also gave acceptable results.
An alternative method would be using a ADC DAC setup. Where the incoming signal gets sampled, stored as a digital number and the DAC would put out a solid voltage forever. Sampling ADC’s these days are far faster then what we could achieve using opamps and jFets and their resolution is good enough to be within a few mV of the original signal. however, such a circuit would be a lot more expensive and introduce some other issues which would have to be taken into account.
Alternatively there are dedicated S&H IC’s which would greatly simplify the circuit while only slightly driving the component price up, but where’s the fun in that.